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Showing posts with label interconnect. Show all posts
Showing posts with label interconnect. Show all posts

Tuesday, September 25, 2012

SoC Bus Architecture Comparison

Rudolf Usselmann compared three SoC buses in OpenCores SoC Bus Review mainly for determining which architecture best suits OpenCores. The article compares IBM CoreConnect, ARM AMBA and Silicon Corp's WISHBONE architectures.

More comparisons are here and here.
Posted by Unknown at 10:19 PM No comments:
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Labels: bus, interconnect, SoC
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